1 / 3 da t a b r ief september 2001 this is brief data from stmicroelectronics. details are subject to change without notice. for complete data, please contact your nearest sales office or smartcard products divison, rousset, france. fax: (+33) 4 42 68 87 29. st19af08 cmos mcu based safeguarded smartcard with 8 kbytes eeprom product features enhanced 8 bit cpu with extended addressing modes 32 kbytes of user rom with partitioning system rom for libraries 960 bytes of user ram with partitioning 8 kbytes of user eeprom with partitioning ? highly reliable cmos eeprom submicron technology ? 10 years data retention ? 100,000 erase/write cycles endurance ? separate write and erase cycles for fast "1" programming ? 1 to 64 bytes erase or program in 1 ms security firewalls for memories very high security features including eeprom flash program and clock management 8 bit timer with interrupt capability 2 serial access, iso 7816-3 compatible 4 general purpose i/os 3v 10% or 5v 10% supply voltage power saving standby mode contact assignment compatible iso 7816-2 unique serial number on each die esd protection greater than 5000v figure 1. delivery form wafer so20 261a.ai
st19af08 2/ 3 hardware description the st19af08, a member of the st19 device family, is a serial access microcontroller especially designed for very large volume and cost competi- tive secure portable objects. the st19af08 is based on a stmicrolectronics 8- bit cpu and includes on chip memories: user rom, user ram and user eeprom with state of the art security features. rom, ram and eeprom memories can be con- figured into partitions with customized access rules. access from any memory area to another is protected by hardware firewalls. access rules are user defined and can be select- ed by mask options or during the life of the prod- uct. it is manufactured using the highly reliable st cmos eeprom submicron technology. as with all the other st19 family members, it is ful- ly compatible with the iso 7816 standards for smartcard applications. software development software development and firmware (rom code/ options) generation are completed by the st19- hdsx development system. figure 2. block diagram 378 internal bus reset serial 8 bit cpu 8 bit clock genera- tor module unpre- system rom firewall memory access firewall clk i/o0 and i/o1 gnd vcc system rom security administrator ram eeprom user rom additional timer user i/o interface i/o dictable number generato r face inter- i/ou0 to i/ou3
3/3 s t 19 af08 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 20 0 1 s t m i c r oe l e c t r o n i c s - a l l r i g h t s re s e r v e d bull cp8 patents stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com
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